FPGA implementation of an efficient graph based algorithm for Electrostatic Discharge (ESD) current path analysis

K.Santosh Kumar1, J.Aditya Varma1, K.Nagashanam1

1ECE Department, MLR Institute of Technology & Management, Hyderabad, A.P., India



The electrostatic discharge (ESD) problem has become a challenging reliability issue in nanometer-circuit design. High voltages that resulted from ESD might cause high current densities in a small device and burn it out, so on-chip protection circuits for IC pads are required. To reduce the design cost, the protection circuit should be added only for the IC pads with an ESD current path, which causes the ESD current path analysis problem. Thus ESD current path analysis algorithm is introduced, which is implemented on FPGA to improve the speed.

          Here the circuit is first modeled as a constraint graph, decompose the ESD connected components (ECCs) linked with the pads, and then identify the ECCs in each constraint graph and, thus, the current paths.

       In this project, architecture for implementing algorithm for ESD current path analysis on FPGA is proposed. The proposed design was coded in VHDL and functionally verified using Modelsim. The design was synthesized on Spartan 3 device xc3s5000 using Xilinx ISE 9.1i. The processor proposed in this thesis achieves more improvement in processing speed as compared to the software implementation. Our architecture can detect all ESD paths in a circuit with eleven nodes in 0.2µs which is 2X105 times faster than implementation of the algorithm in C/C++.






There is growing interest in the effects of Electrostatic Discharge (ESD) on the performance of semiconductor integrated circuits (ICs) because of the impact ESD has on production yields and product quality. ESD problems are increasing in the electronics industry due to trends toward higher speed and smaller device sizes

The phenomenon of ESD exists everywhere in our daily life, such as a standing hair on an electric shock by a door knob. It occurs when an electrostatic voltage develops and discharges as a current impulse. Although ESD includes a little discomfort to humans, it can cause great damage to semiconductor fabrication. In a practical situation, ESD often occurs between two or more devices with different electrostatic potentials, and the current impulses generated by ESD may break circuits and burn devices out [2]. For example for a 0.13µm CMOS

device designed for operation at 1.2V, the voltage drop across a 2Ώ power bus exceeds 20V and burns out the ultrathin gate oxides [3]. As the process technology enters the nanometer era, device size has continued to shrink, and the breakdown voltage of the

thin-oxide devices is usually less than 5V, making the ESD damage occur easily and difficult to prevent [4].

As a result, the prevention of ESD becomes one of the major concerns for IC reliability.

          There are many solutions to the ESD problem [2] examples of which are the use of antistatic coatings to prevent static charge generation in wafers, the use of shielded materials to prevent ESD resulted from human handling, and the implementation of protection circuits within the chip. For the three widely used ESD discharge models [5], [6], we can categorize them into two major classes.

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Volume -01, Issue -05 , December 2013.

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